电源分布系统设计方法论.pdf

Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology Larry Smith, Raymond Anderson, Doug Forehand, Tom Pelc, Tanmoy Roy Sun Microsystems, Inc. MS MPK15-103 901 San Antonio Rd, Palo Alto, CA 94303-4900 larry.smith@, Fax: (650) 786 6457 Abstract Power Systems for modern CMOS technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance vs. frequency profiles of the power distribution system compo- nents including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to spice models. A sufficient number of capacitors are placed in par- allel to meet the target impedance. Ceramic capacitor ESR and ESL are extremely important parameters in determining how many capacitors are required. Spice models are then analyzed in the time domain to find the response to load transients. Introduction Design of the Power Distribution System (PDS) is becoming an increasingly difficult challenge for mod- ern CMOS technology. As CMOS technology is scaled to give smaller and faster transistors, the power supply voltage must decrease. As clock rates rise and more function is integrated into micro processors (µP’s) and application specific integrated circuits (ASIC’s), the power consumed must increase. These trends are summarized for the 1990’s in table 1. Given the voltage and power consumed, the current is calculated from Ohm’s law. Assuming that only a small percentage of the power supply voltage (i.e. 5%) is allowed as ripple voltage (noise), a target impedance for the PDS is calculated. The target im- pedance is falling at an alarming rate, 5X per computer ge