实验六LPM计数器.doc

实验六 LPM计数器 实验名称：LPM计数器 实验过程： 1：调用LPM模块 图1 LPM宏观能块设定 图2 设4位可加减计数器 图3 设定模12计数器，含时钟使能和进位输出 图4 加入4位并行数据预置功能 2：仿真编译： 计数器CNT4B编译 LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY CNT4B IS PORT (aclr,clk_en, clock,sload, updown : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); cout :OUT STD_LOGIC; q :OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END CNT4B; ARCHITECTURE SYN OF cnt4b IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT lpm_counter GENERIC(lpm_direction,lpm_port_updown,lpm_type : STRING; lpm_modulus, lpm_width : NATURAL ); PORT (sload, clk_en, aclr, clock, updown : IN STD_LOGIC ; cout :OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); data : IN STD_LOGIC_VECTOR (3 DOWNTO 0)); END COMPONENT; BEGIN cout = sub_wire0; q = sub_wire1(3 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction = UNUSED, lpm_modulus = 12, lpm_port_updown = PORT_USED, lpm_type = LPM_COUNTER, lpm_width = 4 ) PORT MAP (sload=sload,clk_en=clk_en,aclr=aclr, clock = clock, data = data,updown = updown,cout=sub_wire0,q = sub_wire1); END SYN; CNT4B的例化编译 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY CNT4BIT IS PORT (CLK,RST,ENA,SLD,UD : IN std_logic; DIN : IN std_logic_vector(3 DOWNTO 0); COUT : OUT std_logic; DOUT : OUT std_logic_vector(3 DOWNTO 0)); END ENTITY CNT4BIT; ARCHITECTURE translated OF CNT4BIT IS COMPONENT CNT4B PORT (aclr,clk_en,clock,sload,updown : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END COMPONENT; BEGIN U1 : CNT4B PORT MAP (sload = SLD, clk_en = ENA,aclr = RST, cout=COUT, clock=CLK, data=DIN, updown=UD, q