YuFang（于芳）,andLiuZhongli（刘忠立）.PDF

Vol. 33,No. 1 JournalofSemiconductors January2012 AnIOblock array in a radiation-hardenedSOISRAM-basedFPGA Zhao Yan(赵岩) ,WuLihua(吴利华),Han Xiaowei(韩小炜),Li Yan(李艳), ZhangQianli(张倩莉),Chen Liang(陈亮),Zhang Guoquan(张国全),Li Jianzhong(李建忠), YangBo(杨波),Gao Jiantou(高见头),WangJian(王剑),Li Ming(李明),Liu Guizhai(刘贵宅), ZhangFeng(张峰),GuoXufeng(郭旭峰),Zhao Kai(赵凯),Stanley L. Chen(陈陵都), YuFang(于芳),and Liu Zhongli(刘忠立) Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083,China Abstract: We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field- programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 m partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammablebuffersandtheinput/outputcircuitorasatransparentcircuitwhentheIOBisappliedindifferentmodes. ProgrammableIObufferscanbeusedatTTL/CMOSstandardlevels.Thelocalroutingpoolenhancestheflexibility androutabilityoftheconnectionbetweentheIOBarrayandthecorelogic.Radiation-hardeneddesigns,including A-typeandH-typebody-tiedtransistorsandspecialD-typeregisters,improvetheanti-radiationperformance.The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the corelogiccausedbytheimmensecurrent.ThesedesignstrategiesfacilitatethedesignofFPGAswithdifferentca-