一种I2C总线控制器的接口设计.PDF

第 8 卷 第 4 期 信 息 与 电 子 工 程 Vo1．8，No．4 2010 年 8 月 INFORMATION AND ELECTRONIC ENGINEERING Aug．，2010 文章编号： 1672-2892(2010)04-0467-04 一种 I2C 总线控制器的接口设计 宋 杰，陈 岚，冯 燕 ( 中国科学院 微电子研究所，北京 100029) 摘 要 ：为了实现片上系统芯片与外围设备之间的通信，介绍一种从外围总线(APB) 到 I2C 总 线的接口设计。对整个系统按照功能进行了模块划分，阐述了 APB 总线接口的设计和寄存器配置、 I2C 总线控制器中的状态划分和状态机设计以及时钟产生模块的实现。设计中采用了异步先进先出 来同步 APB 总线和 I2C 总线之间的数据交换。对整个设计进行了功能仿真，实现了系统在 100 kbps 和 400 kbps 两种工作模式下的数据传输。设计完全满足通信的速率要求。 关键词 ：I2C 总线；外围总线；状态机；硬件描述语言 中图分类号 ：TN911.72 文献标识码 ：A An interface design for I2C bus master SONG Jie，CHEN Lan，FENG Yan (Institute of Microelectronics，Chinese Academy of Science，Beijing 100029，China) Abstract： In order to implement communication between System On Chip(SOC) and peripheral device，an interface design for data transfer between Advanced Peripheral Bus(APB) and Inter-Integrated Circuit(I2C) has been proposed in this article. It first describes the function partition of the whole system. Then the APB interface design and register configuration are introduced. The design of main state-machine of I2C bus and the implementation of clock generator are presented. Asynchronous First In First Out(FIFO) is adopted to synchronize data transfer between APB bus and I2C bus. Finally，the functional simulation has shown th at the design performs well in both 100 kbps and 400 kbps. It completely meets the requirement for transfer speed. Key words： I2C bus；Advanced Peripheral Bus；state machine；Verilog HDL