复合逻辑门版图艺术chap4-2-1.ppt

标准单元库 NAND INV A B A Y Y 标准单元库 NAND INV NAND 电路功能：Y=（ABC）’ A B C Y Standard Cell Layout Methodology – 1980s signals Routing channel VDD GND What logic function is this? Standard Cell Layout Methodology – 1990s M2 No Routing channels VDD GND M3 VDD GND Mirrored Cell Mirrored Cell Standard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3? + 3? Pitch = repetitive distance between objects Cell height is “12 pitch” 2? Rails ~10? In Out V DD GND 3? 3? track pitch Standard Cells A Out V DD GND B 2-input NAND gate The design flow ? VHDL (decoder.vhd) Simulation Synthesis Verilog netlist (decoder.v) Place/Route Physical layout (decoder.cif) Standard Cell Lib VHDL Simulator, Now Changes to VCS-MX EE141 * EE141 * Line of diffusion layout – abutting source-drain connections Note crossover of left layout eliminated by A B C ordering – talk about area needed for via (and speed impact due to via resistance) EE141 * Can you draw the Euler diagrams for both and show the consistent Euler path(s) for the second? EE141 * Systematic approach to derive order of input signal wires so gate can be laid out to minimize area Note PUN and PDN are duals (parallel - series) Vertices are nodes (signals) of circuit, VDD, X, GND and edges are transitions EE141 * Consistent Euler paths ABDC BDCA DCAB CABD BACD ACDB CDBA DBAC and NOT DACB, BCAD, etc. EE141 * Can you draw the Euler diagrams for both and show the consistent Euler path(s) for the second? EE141 * EE141 * For lecture Shown synthesis of pull up from pull down structure Max of 3 transistors in series (in the PUN) EE141 * EE141 * 12 and 10 transistor implementations of static XOR circuit EE141 * For class handout EE141 * For lecture 24 + 4 (for C and Sum inverter) transistor Full Adder No more than 3 transistors in series Loads: A-8, B-8, Cin-6, !Cout-2 Number of “gate delays” to Sum – 3? EE141 * EE141 * Route VDD and GND horizontally Route singals in poly perpendicular to VDD and GND (vertic