毕业设计（论文）CMOS PLL锁相环电路设计.doc

PAGE PAGE 19 摘 要 随着通信及电子系统的飞速发展，促使集成锁相环和数字锁相环突飞猛进。 本次毕业设计的主要任务是，采用0.18μm CMOS工艺，设计实现一个基于改进的鉴频鉴相器，压控振荡器，环路滤波器的全集成的CMOS PLL锁相环电路，设计重点为PLL锁相环电路的版图设计，设计工具为Laker。 本论文介绍了PLL锁相环电路的基本原理以及其完整的版图设计结果。本次设计表明，采用该方案实现的锁相环电路主要功能工作正常，初步达到设计要求。 关键词：PLL锁相环电路，鉴频鉴相器，压控振荡器，环路滤波器，版图设计，0.18μm CMOS工艺 Abstract With the development of the communications and electronic systems, the technology of the integrated PLL and digital PLL develops rapidly. The main task of graduation is to design and realize a fully integrated CMOS PLL circuit which is based on an improved phase detector, VCO, loop filter using the 0.18μm CMOS technology. The design focus on the layout of the PLL circuit, and the design tools is the Laker. This paper introduces the basic principles of PLL phase locked loop circuit and its comprehensive layout results. This design shows that the program implemented by the main function of PLL circuit is working well, and it meets the design requirements. Key words: PLL phase locked loop circuits, popularly used phase detectors, discrimination, VCO loop filter, layout design, 0.18 μm CMOS process 目 录 TOC \o 1-3 \h \z \u HYPERLINK \l _Toc289535619 摘 要 PAGEREF _Toc289535619 \h 1 HYPERLINK \l _Toc289535620 Abstract PAGEREF _Toc289535620 \h 2 HYPERLINK \l _Toc289535621 第1章 绪论 PAGEREF _Toc289535621 \h 4 HYPERLINK \l _Toc289535622 1.1 锁相技术的发展 PAGEREF _Toc289535622 \h 4 HYPERLINK \l _Toc289535623 1.2 锁相环路的主要特性 PAGEREF _Toc289535623 \h 4 HYPERLINK \l _Toc289535624 1.3 PLL锁相环的应用领域 PAGEREF _Toc289535624 \h 5 HYPERLINK \l _Toc289535625 第2章 基于CMOS锁相环的电路设计 PAGEREF _Toc289535625 \h 7 HYPERLINK \l _Toc289535626 2.1 锁相环的基本组成 PAGEREF _Toc289535626 \h 7 HYPERLINK \l _Toc289535627 2.2 锁相环工作原理 PAGEREF _Toc289535627 \h 7 HYPERLINK \l _Toc289535628 2.3 鉴相器 PAGEREF _Toc289535628 \h 8 HYPERLINK \l _Toc289535629 2.3.1 鉴频鉴相器（PFD） PAGEREF _Toc289535629 \h 9 HYPERLINK \l _Toc289535630 2.3.2 鉴频鉴相器设计 PAGEREF _Toc289535630 \h 10 HYPERLINK \l _Toc289535631 2.4 环路滤波器 PAGEREF _Toc289535