信号完整性分析_过孔、连接器、封装.ppt

Long package stub effect: Effect of Package: Multi-drop bus topology Long package stub effect Effect of Package: Multi-drop bus topology ADS Simulation ADS Simulation ADS Simulation Vs Zo Zo 0-2V Zo Rs=Zo Vstub RL=Zo Vstubout Vstubin B A C D A B C D 1V 1V -1/3V 2/3V =0.6667V 2/3V 2/3V 2/3V 2/3V=0.6667V 4/3V=2(2/3)V =1.333V (2/3)(-1/3)V=-2/9V -2/9V 4/3V-4/9V =8/9V =0.8889V 4/9V 10/9V =1.111V 4/9V= (2/3)(2/3)V 2/3V+4/9V=10/9V=1.111V Lattice Diagram for Stub Example Interconnect is the path that connects one silicon die (e.g. CPU, chipset, memory…) to another. Silicon has driving and receiving buffers. Vias are vertical metal interconnections that connect different metal layers (within packages and PCB boards and on silicon) Connectors are designed to connect multiple PCB boards Packages have vias and traces designed to interface die and PCB boards PCB boards have vias and traces to connect various component packages. Summary * Variations of Packages Attachment of die to package Wirebond Peripheral I/O location Flip chip, Area Array I/O location Attachment of package to PCB PTH (Pin-Through-Hole), SMT (Surface Mount Technology) I/O locations Peripheral Area Array Package Materials Plastic, Ceramic Thin Film Attachment of die to package Attachment of die to package A ring of bondwire attach pads on the periphery of the face of the die. On the package, the bondwire lands on package routing. A bondwire is about 1mil（25.4um） in diameter, 50-500mils （1.27mm-12.7mm) long. A bondwire acts like an inductor. The die is placed face down. Solder balls attach the on-die pads to the surface of the package. The die pads are not limited to the periphery. The technology is self-aligning because the solder ball surface tension pulls the die pads into alignment with the package pads. Wire bond Flip-chip Pros and Cons to Wire-Bond and Flip-Chip Wire bond Flip-Chip Inductance Much higher (1-5nH) Much less (.1nH) Crosstalk High Virtually none! Cos