验证成功的iic verilog 代码.docx

`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company: kuayuan electronic and teclonogy// Engineer: xiao;//// Create Date: 2012/11/15// Design Name: cyclone IV // Module Name: iic_top// Project Name: iic_project// Target Device: cyclone IV// Tool versions: Quartus 12.0// Dependencies: verilog// // Revision: V1.0// Revision File Created////////////////////////////////////////////////////////////////////////////////moduleiic_project(clk,rst_n,bu1,bu2,scl,sda,LED);inputclk;// 50MHzinput rst_n;// 复位信号，低有效input bu1,bu2;// 按键1、2,(1按下执行写入操作，2按下执行读操作)output scl;// 24C02的时钟端口inoutsda;// 24C02的数据端口output[7:0] LED;// 数码管显示的数据// 按键检测regsw1_r,sw2_r;// 键值锁存寄存器，每20ms检测一次键值reg[19:0] cnt_20ms;// 20ms计数寄存器always @ (posedgeclk or negedgerst_n)if(!rst_n)cnt_20ms = 20d0;elsecnt_20ms = cnt_20ms+1b1;//不断计数always @ (posedgeclk or negedgerst_n)if(!rst_n) beginsw1_r = 1b1;// 键值寄存器初始化为高电平；sw2_r = 1b1;endelse if(cnt_20ms == 20hfffff)beginsw1_r = bu1;//按键1值锁存sw2_r = bu2;//按键2值锁存end//分频部分reg[2:0] cnt; // cnt=0:scl上升沿，cnt=1:scl高电平中间，cnt=2:scl下降沿，cnt=3:scl低电平中间reg[8:0] cnt_delay; //500循环计数，产生iic所需要的时钟regscl_r; //时钟脉冲寄存器always @ (posedgeclk or negedgerst_n)if(!rst_n) cnt_delay = 9d0;else if(cnt_delay == 9d499)cnt_delay = 9d0;//周期为20us，即100KHzelsecnt_delay = cnt_delay+1b1;//时钟计数；always @ (posedgeclk or negedgerst_n)beginif(!rst_n)cnt = 3d5;elsebegincase (cnt_delay)9d124:cnt = 3d1;//cnt=1:scl高电平中间,用于数据采样9d249:cnt = 3d2;//cnt=2:scl下降沿9d374:cnt = 3d3;//cnt=3:scl低电平中间,用于数据变化9d499:cnt = 3d0;//cnt=0:scl上升沿default: cnt = 3d5;endcaseendend`define SCL_POS(cnt==3d0)//cnt=0:scl上升沿`define SCL_HIG(cnt==3d1)//cnt=1:scl高电平中间,用于数据采样`define SCL_NEG(cnt==3d2)//cnt=2:scl下笛?`define SCL_LOW(cnt==3d3)//cnt=3:scl偷缙街屑?用于数据变化always @ (posedgeclk or negedgerst_n)if(!rst_n)scl_r = 1b0;else if(cnt==3d0)scl_r = 1b1;//scl信号上升沿else if(cnt==3d2) scl_r = 1b0;//scl信号下降沿assign scl = scl_r;//产生iic所需要的时钟//需要写入24C02的地址和数据`defineDEVICE_REA