发一个PS2接口的VHDL代码.doc

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发一个PS2接口的VHDL代码

发一个PS2接口的VHDL代码? 贴子发表于:2008/11/16 17:05:47 -- Hi Emacs, this is -*- mode: vhdl -*- ---------------------------------------------------------------------------------- -- Unidirectional PS2 InteRFace (device - host) -- For connect mouse/keyboard -- -- The PS/2 mouse and keyboard implement a bidirectional synchronous serial -- protocol.? The bus is idle when both lines are high (open-collector).? -- THIS A *UNIDIRECTIONAL* INTERFACE (DEVICE - HOST) -- -- Javier Valcarce Garc韆, javier.valcarce@ -- $Id$ ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.utils.all; entity interface_ps2 is ? port ( ??? reset?? : in? std_logic; ??? clk???? : in? std_logic;??????????? -- faster than kbclk ??? kbdata? : in? std_logic; ??? kbclk?? : in? std_logic; ??? newdata : out std_logic;??????????? -- one clock cycle pulse, notify a new byte has arrived ??? do????? : out std_logic_vector(7 downto 0) ??? ); end interface_ps2; ------------------------------------------------------------------------------- architecture behavioral of interface_ps2 is ? signal st : std_logic; ? signal sh : std_logic; ? signal s1?????? : std_logic; ? signal s2?????? : std_logic; ? signal kbclk_fe : std_logic; ? signal shift9 : std_logic_vector(8 downto 0); ? signal error? : std_logic; ? begin ------------------------------------------------------------------------------- -- Edge detector -------------------------------------------------------------------------------? ? process (reset, clk) ? begin ??? if reset = 1 then ????? s1 = 0; ????? s2 = 0; ????? ??? elsif rising_edge(clk) then ????? s2 = s1; ????? s1 = kbclk; ??? end if; ? end process; ? kbclk_fe = 1 when s1 = 0 and s2 = 1 else 0; ------------------------------------------------------------------------------- -- 9-bit shift register to store received data -- 11-bit frame, LSB first: 1 start bit, 8 data

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