静态时序逻辑电路.pptVIP

时钟重叠问题 CLK CLK A B (a)电路图 (b)重叠的一对时钟 X D Q CLK CLK CLK CLK 用伪静态锁存器构成的主从触发器当Clk 和反Clk 发生重迭时，可能引起失效： 当Clk 和反Clk 同时为高时，A 点同时为In 和B 点驱动，造成不定状态 当Clk 和反Clk 同时为高一段较长时间时，In 可以直接穿通经过主从触发器 采用两相位不重迭时钟可以解决此问题，但时钟不重迭部分不能太长以免漏电时间过长引起出错 产生两相不重叠时钟的电路 clk clk1 clk2 A clk A B B clk1 clk2 Power PC的触发器 D Q clk !clk !clk clk 0 1 1 0 1 !clk clk 主 transparent 从 hold 主 hold 从 transparent ?0 ?1 ?0 ?1 低电压静态Latch RS-触发器（flip-flop） 由交叉的NOR ( 或NAND )门构成 S Q R Q CMOS 钟控 SR 锁存器 1 1 0 0 on off off-on off-on ? 0 1 ? on off off on ? on ? on ? off ? off M1 S R clk clk !Q Q M2 M3 M4 M5 M6 M7 M8 0 ? 1 0 ? 1 瞬态响应 Q !Q (Volts) SET !Q Q Time (ns) tc-!Q tc-Q 输出电压与尺寸的关系 W/L5and6 !Q (Volts) W/L2and4 = 1.5?m/0.25 ?m W/L1and3 = 0.5?m/0.25 ?m W/L5and6 3 尺寸问题 输出电压依赖于器件尺寸 瞬态响应 传输管 CMOS SR 锁存器 clk clk S R M1 S R clk !Q Q M2 M3 M4 M5 M6 clk * progressively skew the input wrt to the clock edge until the circuit fails. * the clock is enabled before the nodes on both sides of the transmission gate T2 settle to the same value * Clk and !clk are never perfect inversions of one another – must generate !clk and route both signals (variations can exist in the wires used to route the two clock signals and load capacitances can vary) Clock skew can result in clock overlap * * For lecture 16 transistors with a clock load of 8 (4 on clk and 4 on !clk) – fast and static * For lecture - 8 transistor SR level sensitive latch - two clock loads (sized) No static power consumption, but … Ratioed device where sizing is critical to ensure proper functionality For the case shown, M7 and M8 must succeed in bringing Q low (overcoming M4) - below the threshold of M1 Therefore, must increase the sizes of transistors M5,M6,M7, and M8 * tp!Q = 120 psec tpQ = 230 psec * Want VM at Vdd/2 Assuming Q=0, determine the minimum sizes of M5, M6, M7, and M8 to make the device switchable so the individual device ration for M5 or M6 must be larger than approx. 6. Analysis results give 2.26 (instead of 3) since it doesn’t take into account