VHDL与数字电路设计PPT课件-第五章 组合逻辑电路的设计.ppt

VHDL与数字电路设计 联系电话E-mail：hicx@pcbjut.cn 2005年6月11日 * 电路单元分类 本章内容 基本门电路 编码器和译码器 数据选择器和数据分配器 算术逻辑单元（ALU） 任一时刻的输出仅仅取决于当时的输入，与电路原来的状态无关，这样的数字电路叫做组合逻辑电路。 1、基本门电路 与、或、非门 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY basic_gate IS PORT(a,b: IN std_logic; y1,y2,y3: OUT std_logic); END basic_gate; ARCHITECTURE behave OF basic_gate IS BEGIN y1 = a AND b; y2 = a OR b; y3 = NOT a; END behave; 基本门的行为描述： ARCHITECTURE rtl OF basic_gate IS BEGIN PROCESS(a,b) --与门 VARIABLE ab: std_logic_vector(1 downto 0); BEGIN ab = a b; CASE ab IS WHEN “00” = y1 = ‘0’; WHEN “01” = y1 = ‘0’; WHEN “10” = y1 = ‘0’; WHEN “11” = y1 = ‘1’; END CASE; END PROCESS; …… --或门、非门 END rtl; 基本门的数据流描述： 与非门、或非门、异或门、异或非门 Y1 = NOT (a AND b); Y2 = NOT (a OR b); Y3 = (a AND (NOT b)) OR ((NOT a) AND b); Y4 = NOT Y3; 三态门 EN DIN DOUT DIN EN DOUT X 0 Z 0 1 0 1 1 1 三态门电路的真值表 三态门的VHDL行为描述如下： LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY tristate_gate IS PORT(din,en: IN std_logic; dout: OUT std_logic); END tristate_gate; ARCHITECTURE behave OF tristate_gate IS BEGIN PROCESS(din,en) BEGIN IF (en = ‘1’) THEN dout = din; ELSE dout = ‘Z’; END IF; END PROCESS; END behave; 2.1、编码器: A6 A7 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0 8×3 编码器 A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0 000 001 010 011 100 101 110 111 2、编码器和译码器 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY encoder IS PORT(A : IN std_logic_vector(7 downto 0); Y : OUT std_logic_vector(2 downto 0)); END encoder; ARCHITECTURE rtl1 OF encoder IS BEGIN PROCESS(A) BEGIN IF A= THEN Y= “000”; ELSIF A= THEN Y= “001”; ELSIF A= THEN Y= “010”; ELSIF A= THEN Y= “011”; ELSIF A= THEN Y= “100”; ELSIF A= THEN Y= “101”; ELSIF A= THEN Y= “110”; ELSIF A = THEN Y= “111”; ELSE Y= “