VHDL与数字电路设计PPT课件-第六章 时序逻辑电路的设计.pptVIP

上升沿翻转的8分频器 下降沿翻转的8分频器 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY FreDevider IS PORT(clkin: IN std_logic; clkout: OUT std_logic); END FreDevider; ARCHITECTURE rtl OF FreDevider IS SIGNAL counter: integer RANGE 0 TO 2; SIGNAL tmp1,tmp2: std_logic; BEGIN PROCESS(clkin) BEGIN IF rising_edge(clkin) THEN IF counter=2 THEN counter = 0; tmp1 = NOT tmp1; ELSE counter = counter+1; END IF; END IF; IF falling_edge(clkin) THEN IF counter=1 THEN tmp2 = NOT tmp2; END IF; END IF; END PROCESS; clkout = tmp1 XOR tmp2; END; 奇数倍分频电路（3分频） 6、存储器 256X8 ROM g1 g2 addr7~addr0 data_out7~data_out0 容量为256X8的ROM 当g1=‘1’且g2=‘1’时，存储器将把根据地址线选中的存储单元中的数据送到输出数据线上；否则输出数据线呈现高阻状态。 LIBRARY IEEE; USE IEEE.std_logic_1164.all; Use IEEE.std_logic_unsigned.all; ENTITY rom256_8 IS PORT(addr: IN std_logic_vector(7 DOWNTO 0); g1, g2: IN std_logic; data_out: OUT std_logic_vector(7 DOWNTO 0)); END rom256_8; ARCHITECTURE rtl OF rom256_8 IS SUBTYPE word IS std_logic_vector (7 DOWNTO 0); TYPE memory IS ARRAY (0 TO 255) OF WORD; SIGNAL rom : memory := (--初始化数据，省略); SIGANL addr_in: integer RANGE 0 TO 255; BEGIN PROCESS(g1,g2,addr) BEGIN addr_in = conv_integer(addr); IF(g1=‘1’ AND g2=‘1’) THEN data_out = rom(addr_in) ELSE data_out = (OTHERS = ‘Z’); END IF; END PROCESS; END rtl; 256X8 RAM cs wr addr7~addr0 data_out7~data_out0 容量为256X8的RAM 当… rd data_in7~data_in0 LIBRARY IEEE; USE IEEE.std_logic_1164.all; Use IEEE.std_logic_unsigned.all; ENTITY ram256_8 IS PORT(addr: IN std_logic_vector(7 DOWNTO 0); data_in: IN std_logic_vector(7 DOWNTO 0); wr,rd,cs: IN std_logic; data_out: OUT std_logic_vector(7 DOWNTO 0)); END ram256_8; ARCHITECTURE rtl OF ram256_8 IS SUBTYPE word IS std_logic_vector (7 DOWNTO 0); TYPE memory IS ARRAY (0 TO 255) OF WORD; SIGNAL sram : memory; SIGANL addr_in: integer RANGE 0 TO 255; BEGIN addr_in = conv_integer(addr); PROCESS(wr) BEGIN IF(wr’event AND wr=‘1’) THEN IF