Microchip PIC32MZ系列连接解决方案.docxVIP

Microchip PIC32MZ系列连接解决方案Microchip公司的PIC32MZ EF系列采用MIPS32? M级核,工作频率200MHz,性能高达330DMIPS,FPU适用于快速单和双精密算法,MMU适用于优化嵌入式OS执行,microMIPS?模式可缩减代码尺寸高达35%,具有增强DSP核,四个64位累加器,IEEE-754兼容,有更佳的性能,浮点单元,容量更大的闪存以及多种连接选项和丰富的外设集，有助于嵌入式开发人员满足新一代高端应用不断增长的需求.本文介绍了PIC32MZ处理器主要特性和PIC32MZ EF系列微处理器核主要特性与框图,PIC32MZ EF入门套件DM320007主要特性,框图,电路图和材料清单.The MIPS32? M-Class Core is the heart of the PIC32MZ EF family device processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations.PIC32MZ EF系列微处理器核主要特性:?5-stage pipeline?32-bit address and data paths?MIPS32 Enhanced Architecture (Release 5):-Multiply-accumulate and multiply-subtract instructions?-Targeted multiply instruction-Zero/One detect instructions-WAIT instruction-Conditional move instructions (MOVN, MOVZ)-Vectored interrupts-Programmable exception vector base-Atomic interrupt enable/disable-GPR shadow registers to minimize latency for interrupt handlers-Bit field manipulation instructions-Virtual memory support?microMIPS? compatible instruction set:-Improves code size density over MIPS32, while maintaining MIPS32 performance.-Supports all MIPS32 instructions (except branch-likely instructions)-Fifteen additional 32-bit instructions and 39 16-bit instructions corresponding to commonly-used MIPS32 instructions-Stack pointer implicit in instruction-MIPS32 assembly and ABI compatible?MMU with Translation Lookaside Buffer (TLB) mechanism:-16 dual-entry fully associative Joint TLB-4-entry fully associative Instruction and Data TLB-4 KB pages?Separate L1 data and instruction caches:-16 KB 4-way Instruction Cache (I-Cache)-4 KB 4-way Data Cache (D-Cache)?Autonomous Multiply/Divide Unit (MDU):-Maximum issue rate of one 32x32 multiply per clock-Early-in iterative divide. Minimum 12 and maximum 38 clock latency (dividend (rs) sign extension-dependent)?Power Control:-Minimum frequency: 0 MHz-Low-Power mode (triggered by WAIT i