A Nonlinear Phase Frequency Detector for Fast Lock英文电子书.pdf

A Nonlinear Phase Frequency Detector for Fast-Lock Phase-Locked Loops Jinbao Lan * , Fengchang Lai, Zhiqiang Gao, Hua Ma and Jianwei Zhang Abstract - A new nonlinear phase frequency detector The transfer characteristic of the nonlinear PFD proposed (PFD) ispresented in this paper. When the phase error is not by [5] is demonstrated in Fig.2, of which the Y-axis represents less than TC, the proposed PFD has a constant output and so a the average output current of the charge pump. When the nonlinear gain to accelerate the lock acquisition of a phase- input phase error ~qJ detected by the PFD is larger than a locked loop (PLL); when the phase error is less than TC, the predefined value tpd a larger PFD gain of (Icr + I d ) / 27r proposed PFD has a linear gain just like the conventional PFD to make the PLL maintain a proper loop bandwidthfor is used to obtain a wider loop bandwidth (PLL loop low outputjitter. A circuit embodiment of the proposed PFD, bandwidth me oc K PFD [7]) and resultantly faster lock. which uses the same amount oftransistors as the conventional When I~ tp I~ tpd a smaller linear PFD gain of I cr / 27r is PFD circuit does, is also presented. Circuit simulation results show that the proposed PFD circuit accelerates the lock used to maintain a narrower loop bandwidth and as a result better jitter suppression. Though