A Second Order Double Sampled Delta Sigma Modulator Using Additive Error Switching英文电子书.pdf

284 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 3, MARCH 1996 ssue Papers ouble-Sampled De Additive-Error Switching Ted Vinko Burmas, Member, IEEE, Kenneth C. Dyer, Student Member, IEEE, Paul J. Hurst, Senior Member, IEEE, and Stephen H. Lewis, Member, IEEE Abstruct- A second-order double-sampled delta-sigma mod- input and changes only when the sampling capacitor dumps ulator is described. It uses an additive-error switching scheme charge to its integrating capacitor. To overcome this limitation, to convert capacitor mismatch into an additive out-of-band tone two sampling capacitors can be used for each integrating that can be removed by a digital filter. With a sampling rate of 5 MHz and an oversampling ratio of 256, the maximum measured capacitor. If the two sampling capacitors are time interleaved, signal-to-noise-and-distortionratio (SNDR) is 86.3 dB, and the one samples the input and the other dumps charge onto the total harmonic distortion is -88.7 dB when the input is 2 dB integrating capacitor during each clock phase [4]. Therefore, below full scale. The modulator is fully differential, occupies 5 this approach doubles the ACM sample rate without requiring mm2, and dissipates 13 mW. faster op-amps, and this increase can be used to increase the baseband signal-to-noise ratio (SNR).