Design of charge pump circuit with consideration of gate oxide reliability in low voltage CMOS processes英文电子书.pdf

1100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006 Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes Ming-Dou Ker, Senior Member, IEEE, Shih-Lun Chen, Student Member, IEEE, and Chia-Shen Tsai Abstract—A new charge pump circuit with consideration of gate- oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping ef- ficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal oper- ating power supply voltage (VDD). Two test chips have been imple- mented in a 0.35- m 3.3-V CMOS process to verify the new pro- posed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3 3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping effi- ciency and no overstress across the gate oxide of devices. Index Terms—Body effect, charge pump circuit, gate-oxide reli- ability, high-voltage generator, low voltage. Fig. 1. Four-stage (a) diode and (b) Dickson charge pump circuits. I. INTRODUCTION HARGE pump circuits have been often used to generate Cdc voltages those are higher than the normal power supply