具有时间隐藏特性的数据块读写SDRAM 控制器.pdf

35 4 2009 2 Vol.35 No.4 Computer Engineering February 2009 ·· 2009 A TP333 SDRAM ( 410073) SDRAM SDRAM FPGA 44 52%88 44% SDRAM SDRAM Controller with Time-hiding Feature for Data Block Access WANG Bin, XIONG Zhi-hui, CHEN Li-dong, TAN Shu-ren, ZHANG Mao-jun (College of Information Systems and Management, National University of Defense Technology, Changsha 410073) AbstractIn order to speed up the efficiency of SDRAM controller while reading/writing data blocks, this paper proposes a time-hiding method for the design of SDRAM controller. It implements this method on FPGA. Experiments indicate that this time-hiding method shortens the latency and increases the speed of accessing data blocks. For example, when writing 44 data blocks, this method saves access time by 52%, and when reading 88 data blocks, this method saves access time by 44%. Key wordstime-hiding; data block; SDRAM controller 1 SDRAM (1) 0 READ ACTIVE Bank row ACTIVE SDRAM [1] READ tRCD READ Bank [2]Bank CL 0 [3]SDRAM ACTIVE [4][5] T_bf_d(Time before data) T_d_v(Time of data valid) MT48LC4M32B2-7 [6]HDTV SDRAM 32 bitT_d_v Bank SDRAM m [2] Bank (2) 0 PRECHARGE [3] row 1 row [4][5] PRECHARGE tRP