AT24C128B(汽车用串行存贮芯片资料ATMEL).pdfVIP

1. Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 3.6V) • Internally Organized as 16,384 x 8 • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (3.6V, 2.5V), and 400 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 64-byte Page Write Mode (Partial Page Writes Allowed) Two-wire Serial • Self-timed Write Cycle (5 ms Max) EEPROM • High Reliability – Endurance: One Million Write Cycles – Data Retention: 40 Years 128K (16,384 x 8) • Lead-free/Halogen-free • 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Thin Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages AT24C128B • Die Sales: Wafer Form, Tape and Reel and Bumped Wafers 2. Description The AT24C128B provides 131,072 bits of serial electrically erasable and programma- ble read-only memory (EEPROM) organized as 16,384 words of 8 bits each. The Preliminary device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (1.8V to 3.6V) version. Table 0-1. Pin Configurations 8-lead PDIP 8-lead SOIC Pin Name Function