数电课件Lec03-Chap3.ppt.ppt

Back ups * * Quiz A 74LS00 has VOHmin=2.7V, VOLmax=0.5V, VIHmin=2.0V, VILmax=0.8V, determine the worst-case LOW-state and HIGH-state DC noise margins of the 74LS00. 3.5.6 How to destroy a CMOS device Stray capacitance (寄生电容) Electrostatic discharge(ESD 静电放电) * + - Jin. UESTC Digital Logic Design and Application Jin. UESTC * Digital Logic Design and ApplicationChenYanLecture #3 CMOS Electrical Behavior UESTC, Spring 2014 * 3.4 Electrical Behavior of CMOS Circuits Digital analysis works only if circuits are operated in spec.: Power supply voltage Temperature Input-signal quality Output loading Must do some “analog” analysis to prove that circuits are operated in spec. Fan-in specs Fan-out specs Timing analysis (setup and hold times) * 3.4 Electrical Behavior of CMOS Circuits Overview Logic Voltage Levels DC Noise Margins Fan-Out Speed Power Consumption Noise Electrostatic Discharge (静电放电) * 3.4 Electronic Behavior of CMOS Circuits A NAND Gate Data Sheets and Specifications (P99 Table 3-3) * 3.5 CMOS Steady-State Electrical Behavior 3.5.1 Logic Levels and Noise Margins VDD = +5.0V VOUT VIN Tp Tn 0 and 1 0 1 and 静态; 稳态 The input voltages are determined mainly by switching thresholds of the transistors the output voltages are determined mainly by the “on” resistance of the transistors. * 输入/出电压转移曲线越陡，电路的噪声容限越大。 HIGH ABNOMAL LOW VOLmax VOHmin VILmax VIHmin VCC?0.1V GND+0.1V 70%VCC 30%VCC Power-supply rails: VCC and GND * 3.5.1 DC Noise Margin 30%VCC ? 0.1V HIGH ABNOMAL LOW VOLmax VILmax VIHmin VOHmin High-state DC noise margin Low-state DC noise margin 3.5 CMOS Steady-State Electrical Behavior 3.5.2 Circuit Behavior with Resistive Loads Resistive Loads discrete resistor TTL and other non-CMOS load Current consumption device * which require nontrivial amounts of current to operate CMOS device has very high input impedance, it behaves as ideal logic device. 3.5.2 Circuit Behavior with Resistive Loads * When the output of CMOS ci