国外 计算机课件 Hardware.ppt

  1. 1、本文档共15页,可阅读全部内容。
  2. 2、有哪些信誉好的足球投注网站(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
国外 计算机课件 Hardware

Computer Architecture Computer Hardware Electronic Components Electromechanical Devices Software Instruction and data that the computer manipulates to perform various data processing task Block Diagram of Digital Computer Hardware Central Processing Unit(CPU) Arithmetic Logic Unit Registers-Holding data Fetch and Execute Control Circuits Random Acess Memory (RAM) Input Output Processors(IOP) Transfers data between Computer and Outside World. Example :Keyboard,Printers etc Definitions Computer Architecture: Is those Attributes Visible to the Programmer Instruction set Addressing Technique Numbers of bits used for data representation IS THERE A MULTIPLY INSTRUCTION Cont’ Computer Organization Is How Features are Implemeted Control Signals,interfaces,Memory technology IS THERE A HARDWARE MULTIPLY UNIT OR IS IT DONE BY REPEATED ADDITION Central Processing Unit Major Components of CPU Register Set Holds Intermediate data used during Instruction Execution ALU Perform Micro operations for Executing Instructions Control Unit Supervises data transfers among registers Tells ALU which operation to Perform Cont’ General Register Organization Cont’ Bus Organization for seven CPU Registers Output of Each register is Connected to Two Multiplexers(MUX) to form the two buses A B The selection line in MUX select one register or the input data for the particluar bus Cont’ A B form the give input to ALU Operations is Selected in the ALU Result of the micro operation is available in Output data also goes in to the input of all registers Cont’ The register that receives the information from output bus is selected by a decoder Decoder activates one of the register load inputs thus provide a data transfer between the data in the output bus and the inputs of the selected destination register Example –R1-R2+R3 MUX A selector (SELA) Put Content of R2 on bus A MUX B selector (SELB) Put Content of R3 on bus B ALU operation selector(OPR) Perform Arithmetic Addition A+B

文档评论(0)

153****9595 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档