using intellion′s serial peripheral interface.pdf

Application Note #0069 Using Intellon’s Serial Peripheral Interface Introduction This document is intended to aid software engineers in the design of firmware compatible with Intellon’s Serial Peripheral Interface (SPI) used, for example, on the SSC P200 and P300. The SPI supports the transmission and reception of data packets, and provides read or write capability for data link control parameters. This document discusses the hardware interface needed to communicate with the network interface chip. Further, software issues concerning Motorola’s SPI and a general I/O port “bit-bang” method are discussed. Hardware Interface There are 5 I/O lines and one reset line used by the SPI. These are INT*, CS*, SCLK, SDI, SDO, and RST*. Their description is given below: INT* - The network interface chip pulls this line low whenever service from the host is required. The three most common conditions that generate an interrupt are packet received, packet transmission complete, and SPI byte transfer complete. CS* - The host pulls the chip select line low to start communication with the network interface chip. This line remains low during the read or write operation which is called a transaction. The host sets this line high when the transaction is complete. SCLK - The host generates a clock signal to synchronize the data transfer. When the host is writing data, the network interface chip reads the data on the rising edge of the clock. When the host is reading data, the network interface chip places data on serial data output (SDO) pin on the falling edge of the clock and the host reads the data on the rising edge of the clock. See the data sheet for the setup and hold times. SDI - The data generated by the host is placed on this line and clocked into the network interface