EDA技术与应用教学（张静秋）第7-8讲 组合电路设计.pdfVIP

第7-8讲组合电路设计 1. 基本逻辑门的VHDL描述 2. 译码器的VHDL描述 3. 编码器的VHDL描述 4. 多路分配器的VHDL描述 5. 数值比较器的VHDL描述 6. 加法器的VHDL描述 7. 三态缓冲器的VHDL描述 【例1】基本逻辑门的描述 【或门逻辑描述示例】 LIBRARY IEEE ; 其它基本逻辑门： USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS 1) y= a nand b; PORT (a, b : IN STD_LOGIC; 2) y= a nor b; c : OUT STD_LOGIC ); END ENTITY or2a ; 3) y= a xor b; ARCHITECTURE one OF or2a IS BEGIN c = a OR b ; END ARCHITECTURE one; 【或门逻辑描述示例】 编译结果 【例2】 3-8译码器设计之一 Entity decoder38 is port(a,b,c,s1,s2,s3: in std_logic; y : out std_logic_vector( 7 downto 0 )); End decoder38; Architecture behave38 OF decoder38 is Signal indata: std_logic_vector(2 downto 0); Begin indata=cba; Process(indata,S1,S2,S3) begin If (s1=1 and s2=0 and s3=0) then Case indata is when “000“ = y = ; --原码输入 when “001“ = y = ; --输出低电平有效 when 010“ = y = when 011“ = y = when 100“ = y = when 101“ = y = when 110“ = y = when 111“ = y = when others= y = XXXXXXXX; End case; else y = End if; End process ; End behave38; 【例2】3-8译码器设计之一 仿真结果 【例2: 3to8 decoder设计之二】 --利用转换函数实现 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder3to8 IS PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder3to8; ARCHITECTURE behave OF decoder3to8 IS BEGIN PROCESS (input) BEGIN output = (OTHERS = 0); output( CONV_INTEGER (input)) = 1; END PROCESS;