数模转换基础.ppt

* * *07/16/96 * *## DAC outputs a digital code to relate analog input, after trigger or clock are inputted. DAC specification has term of ‘settling time’, it is a time interval from output signal changed until output will be stable from . We should measure a output value when signal is stable, so we should wait among settling time. In this figure, it give a code to DAC, to count up 1LSB from code 0.It waits settling time, then it measures a output. * INL = ILE DLE = DNL * DAC Test DAC Test DAC Test Static Test DAC Static Performance Specifications DAC Test Methodology Dynamic Test DAC Dynamic Performance Specifications DAC Test Methodology DAC Test Ideal vs. Real DAC Digital input code Discrete Analog Output Voltage Digital input code Discrete Analog Output Voltage Ideal DAC Non-Ideal DAC Ideal Linear DAC Transfer Diagram Analog Output Value Digital Input Code Ideal Straight Line DAC Transfer Function 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 8 Step Height (1 LSB) Step Value Nominal Full-scale 3-bit DAC Practical Full-scale Practical Full-scale Nominal Full-scale DAC Static Performance Specifications Differential Non-Linearity (DNL) Integral Non-Linearity (INL) Offset Error Gain Error Gain Mismatch DAC Differential Non-Linearity, DNL DNL is the deviation of the actual step size from the ideal step size of 1 LSB. It is expressed in fractions of 1 LSB. For an ideal DAC, DNL is zero. Digital Input code Discrete Analog Output Voltage Deviation 1 LSB 1 LSB Deviation Measured Values Ideal Value after 1 LSB Step where i = 1, 2, ... 2n–1 1 2 3 Intepretating DC Transfer Characteristics Zero point method – assumes that the middle sample is correct and then minimizes the mean error Digital Input code Discrete Analog Output Voltage V[ns/2] Digital Input code Discrete Analog Output Voltage Minimum RMS method – minimizes the mean, averaged deviation ns = # of sampled points End point method – assumes a straight line between first and last sample Digital In