[信息与通信]vlsi circuit design 02 cmos inverter hit.ppt

CMOS Inverter Review: Design Abstraction Levels Review: The MOS Transistor The Inverter, A Static View CMOS Inverter: A First Look CMOS Inverter: Steady State Response CMOS Properties Full rail-to-rail swing ? high noise margins Logic levels not dependent upon the relative device sizes ? transistors can be minimum size ? ratioless Always a path to Vdd or GND in steady state ? low output impedance (output resistance in k? range) ? large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) ? nearly zero steady-state input current No direct path steady-state between power and ground ? no static power dissipation Propagation delay function of load capacitance and resistance of transistors Review: Short Channel I-V Plot (NMOS) Review: Short Channel I-V Plot (PMOS) Transforming PMOS I-V Lines CMOS Inverter Load Lines CMOS Inverter Voltage Transfer Characteristics (VTC) CMOS Inverter Voltage Transfer Characteristics (VTC) CMOS Inverter: Switch Model of Dynamic Behavior CMOS Inverter: Switch Model of Dynamic Behavior Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics Switching Threshold VM where Vin = Vout (both PMOS and NMOS in saturation since VDS = VGS) VM ? rVDD/(1 + r) where r = kpVDSATp/knVDSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want VM = VDD/2 (to have comparable high and low noise margins), so want r ? 1 (W/L)p kn’VDSATn(VM-VTn-VDSATn/2) (W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2) Switch Threshold Example In our generic 0.25 micron CMOS process, using the process parameters from slide L03.25, a VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5) Switch Threshold Exam