[信息与通信]数字逻辑第5章.ppt

always @ (a or b or state)begin//next logic case (state) init: if (a==0) excite=a0; else excite=a1; a0: if (a==0) excite=ok0; else excite=a1; a1: if (a==0) excite=a0; else excite=ok1; ok0: if (a==0) excite=ok0; else if ((a==1) (b==0)) excite=a1; else excite=ok1; ok1: if (a==1) excite=ok1; else if ((a==0) (b==0)) excite=a0; else excite=ok0; default: excite=init; endcase end always @ (posedge clk)begin //state reg state= excite;end always @ (state)begin //output logic case (state) init,a0,a1: z=0; ok0,ok1: z=1; default z=0; endcase end endmodule FSM design module k74163 (clk,clr,ld,enp,ent,d,q,rco); input clk,clr,ld,enp,ent; input[3:0] d; output rco; output[3:0] q; reg rco; reg[3:0] q; Binary counter design always @ (posedge clk) begin if(clr==0) q=4b0000; else if(ld==0) q=d; else if((ent==1)(enp==1)) q=q+1; else q=q; end always @(q or ent) begin if((ent==1)(q==4b1111)) rco=1; else rco=0; end endmodule Binary counter design 请同学们自己仿真第八章的各MSI器件的逻辑功能 课程设计 题目1： 题目2： Chapter 5 Hardware Description Language Verilog HDL structure Signal and operations Structure description Behavioral decription Verilog HDL structure Hardware module： Name、port and structure; Verilog HDL structure module majority (a,b,c,f); input a,b,c; output f; … structure description; … endmodule One bit signals’ declare: Verilog 的关键字：只使用小写字母； 用户定义的标识符：可以大写字母，也可以小写字母，但大小写代表不同的标识符。 Verilog HDL structure module inhibit (a,b,s); input [3..0] a,b; output [8..0] s; … structure description; … endmodule multibit or vector signals’ declare: Signal and operations Two kinds of signal : port : input and output; wire : any connect nets in module; The value of signals (four-valued ): 0: logic 0 1 : logic 1 z: high inpedance x: an unknown logic value Verilog HDL structure module maj