[信息与通信]第2章_VHDL设计初步.ppt

etret 第2章 本章重点将介绍VHDL基本的语法结构 ◆ 什么是VHDL？ Very high speed integrated Hardware Description Language (VHDL) 是IEEE、工业标准硬件描述语言 用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 特别适合于设计的电路有： 复杂组合逻辑电路，如： 译码器、编码器、加减法器、多路选择器、地址译码器…... 状态机 等等…….. - VHDL is what you write is what functional you get “ tell me how your circuit should behave and the VHDL compiler will give you the hardware that does the job” but the designer can not control how the circuit implement ◆ 原理图输入与 VHDL文本输入设计的区别 - Graphic is what you draw is what you get “ tell me what hardware you want and I will give it to you” ◆ VHDL的功能和标准 VHDL 描述 输入端口 输出端口 电路的行为和功能 VHDL有过两个标准： IEEE Std 1076-1987 (called VHDL 1987) IEEE Std 1076-1993 (called VHDL 1993) ◆ Why using VHDL instead of Graphic Easy to Modify It is more powerful than Graphic VHDL is a portable language because is device independent the same code can be applied to Device manufactured by Company A or Company B 【例2-1】 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21a IS PORT( a, b : IN BIT ; s : IN BIT; y : OUT BIT ) ; END ENTITY mux21a ; ARCHITECTURE one OF mux21a IS BEGIN y = a WHEN s = 0 ELSE b ; END ARCHITECTURE one ; 实体 结构体 2.1 多路选择器VHDL描述 图2-1 mux21a实体 图2-2 mux21a结构体 2.1.1 2选1多路选择器的VHDL描述 IEEE库使用说明 2.1.1 2选1多路选择器的VHDL描述 【例2-2】 ENTITY mux21a IS PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS SIGNAL d,e : BIT; BEGIN d = a AND (NOT S) ; e = b AND s ; y = d OR e ; END ARCHITECTURE one ; 【例2-3】 . . . ARCHITECTURE one OF mux21a IS BEGIN y = (a AND (NOT s)) OR (b AND s) ; END ARCHITECTURE one; 2.1.1 2选1多路选择器的VHDL描述 【例2-4】 ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN PROCESS (a,b,s) BEGIN IF s = 0 THEN y = a ; ELSE y = b ; END IF; END PROCESS; END ARCHITECTURE one ; 2.1.1 2选1多路选择器的VHDL描述 图2-3 mux21a功能时