ispLever使用教程.pptVIP

下载 2、VHDL的原理图方式设计 （八）ISPLEVER 软件的使用方法 点击File —New Project 选器件 点击下一步 点击完成 点击Source —New 后面的操作同前 作业：用VHDL语言： 1、设计一个3线－8线译码器； 2、设计一个上升沿触发JK触发器。 CLR J Q K library ieee; use ieee.std_logic_1164.all; entity dff1 is port(clk,d:in std_logic; q:out std_logic); end; architecture rtl of dff1 is begin process(clk) begin if(clkevent and clk=1)then q=d; end if; end process; end rtl; library ieee; use ieee.std_logic_1164.all; entity and_gate is PORT(A,B:IN std_logic;X:OUT std_logic); end; architecture rtl of and_gate is begin X=A AND B; end rtl; library ieee; use ieee.std_logic_1164.all; entity decoder_38 is PORT(input:IN std_logic_vector(2 downto 0); output:OUT std_logic_vector(7 downto 0)); end; architecture rtl1 of and_gate is begin X=A AND B; end rtl1; library ieee; use ieee.std_logic_1164.all; entity decoder is PORT(input:IN std_logic_vector(2 downto 0); output:OUT std_logic_vector(7 downto 0)); end; architecture rtl1 of decoder is begin process(input) case input is when 0=output when 1=output when 2=output when 3=output when 4=output when 5=output when 6=output when 7=output end case; end process; end rtl1; library ieee; use ieee.std_logic_1164.all; entity decoder is PORT(input:IN std_logic_vector(2 downto 0); yout:OUT std_logic_vector(7 downto 0)); end; architecture rtl1 of decoder is begin process(input) case input is when 000=yout when 001=yout when 010=yout when 011=yout when 100=yout when 101=yout when 110=yout when 111=yout end case; end process; end rtl1; library ieee; use ieee.std_logic_1164.all; entity ym3_8 is port(a:in std_logic_vector(2 down