ch7-物理设计.pptVIP

Route Clock Nets First Core Routing: route_opt First route_opt Post Route Optimization Examples Verify Route: verify_zrt_route Unit6 Reporting the Critical Area Solution: Wire Spreading + Wire Widening Fix Remaining Antenna Violations w/ Diodes Antenna Fixing with Diode Insertion Insert Filler Cells in Unused Placement Sites Incremental Timing Optimization Redundant Via Insertion Timing Preservation Mode Insert Metal Fill to Prevent Over-Etching Final Validation Final Validation(2) Parasitics (SPEF or SBPF) Netlist Output GDSII Output Analyze Timing Violations Paths are Grouped for Efficient Optimization Incremental Logic Optimization: psynopt Enable Global Router During Optimization If the design is still seriously congested? Improve Congestion/Setup Timing Placement Unit4 芯片中的时钟网络要驱动电路中所有的时序单元，所以时钟负载延时很大并且不平衡，需要插入缓冲器减小负载和平衡延时。 时钟网络及其上的缓冲器构成了时钟树。 CTS的目的是为了减小时钟偏差（clock skew） 时钟信号定义 SDC CTS策略 时钟树分析 Clock Tree Synthesis Starting Point before CTS All clock pins are driven by a single clock source. Clock Tree Synthesis (CTS) A buffer tree is built to balance the loads and minimize the skew. Delay Cells Are Added to Meet Min. Insertion Control Buffer/Inverter Selection Remove “Skew” from Uncertainty Non-Default Routing Rules Defining and Applying NDR Rule Example Default Routing Rule for Sink Pins Option clock_opt clock_opt Functionality Analyzing CTS Results Enable Hold Time Fixing CTS Unit5 布线是继布局和时钟树综合之后的重要物理实施任务，其内容是将分布在芯片核内的模块、标准单元和输入输出接口单元（I/O pad）按逻辑关系进行互连，其要求是100%地完成他们之间的所有逻辑信号的互连，并为满足各种约束条件进行优化。 Routing 进行消除布线拥塞（congestion）、优化时序、减小耦合效应（coupling）、消除串扰（crosstalk）、降低功耗、保证信号完整性（signal integrity）、预防DFM问题和提高良品率等布线的优化工作是衡量布线质量的重要指标。 Routing VLSI电路多层布线采用自动布线方法，在实施过程中，它被分为全局布线（global routing）、详细布线（detail routing）和布线修正（search and repair）三个步骤来完成。自动布线的质量依赖于布局的效果以及EDA工具所采用的布线算法和优化方法。 Set Common Route Options Set Global Route Options Set Track Assignment Options Set Detail Route Options Antenna Violations Fixing Antenna Violation by Layer Jumping Define Routing Blocka