[工学]05_Altera器件的推荐代码风格.ppt

Recommended Coding Styles for Altera Devices Agenda Objectives Inferring Logic Functions Instantiating Logic Functions Writing Efficient Verilog Coding State Machines Optimizing Designs for FPGA Recommended Coding Styles for Altera Devices Objectives Objectives Build the mindset of writing Verilog codes targeting PLD devices Get knowledge of Altera-recommended Verilog coding styles Avoid Verilog codes hurting efficiency in terms of resource usage, timing performance, power consumption, etc. Recommended Coding Styles for Altera Devices Inferring Logic Functions Modeling for Synthesis Design methodology uses synthesis tool to convert RTL code to library cells Code is interpreted hardware created Knowledge of FPGA architecture is helpful Synthesis tools require certain coding to generate correct logic Subset of Verilog language supported The goals of coding style are efficiency and predictability Pre- post-synthesis logic should operate the same Inferring Logic Functions Using behavioral modeling to describe logic blocks e.g. Latches, registers, counters, tri-states, memory, arithmetic Synthesis tools recognize description insert logic functions Functions typically pre-optimized for utilization or performance Makes code vendor-independent Logic Inference Inferring Tri-States Bidirectional Pins Inferring Latches Inferring Flip-flops Inferring Flip-flops A Case for Incorrect Control Logic DFF with Clock Enable Shift Registers Counter w/Clock Enable Memory Synthesis tools have different capabilities for recognizing memories Synthesis tools are sensitive to certain coding styles in order to recognize memories Usually described in the tool documentation (e.g. “Inferring Memory Functions from HDL Code” in Quartus II Handbook, Volume 1) Must declare an array data type to hold memory values Inferred Single-Port Memory Inferred Dual-Port Memory Recommended Coding Styles for Altera Devices Instantiating Logic Functions Instantiating Logic Functions Using structural modeling