[信息与通信]tutorial_quartusii_intro_verilog.pdf

Quartus® II Introduction for Verilog Users This tutorial presents an introduction to the Quartus® II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by using FPGA devices, and shows how this flow is realized in the Quartus® II software. The design process is illustrated by giving step-by-step instructions for using the Quartus® II software to implement a simple circuit in an Altera® FPGA device. The Quartus® II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system. This tutorial makes use of the Verilog design entry method, in which the user specifies the desired circuit in the Verilog hardware description language. Another version of this tutorial is available that uses VHDL hardware description language. The screen captures in the tutorial were obtained using Quartus® II version 9.0; if other versions of the soft- ware are used, some of the images may be slightly different. Contents: Getting Started Starting a New Project Design Entry Using Verilog Code Compiling the Verilog Code Using the RTL Viewer Specifying Timing Contraints Quartus® II Windows Computer Aided Design (CAD) software makes it easy to implement a desired logic circuit by using a pro- grammable logic device, such as a field-programmable gate array (FPGA) chip. A typical FPGA CAD flow is illustrated in Figure 1. Design Entry Synthesis Functional Simulation No Design correct? Yes