[信息与通信]DigitalDesignandComputerArchitecturePipeline.ppt

Review: Instruction Formats Review：Instruction Execution Flow Review: Single-Cycle MIPS Processor Review: Multicycle MIPS Processor Pipelined MIPS Processor Single-Cycle vs. Pipelined Performance Pipelining Abstraction Single-Cycle and Pipelined Datapath Corrected Pipelined Datapath Pipelined Control Pipeline Hazard Structrual Harzard: one port MEM Structural Harzard: Stall Data Harzard on R1 Types of Data Harzards Data harzards on “R1” Handling Data Hazards Compile-Time Hazard Elimination Data Forwarding/Bypassing 前推 旁路 Data Forwarding Data Forwarding Data Forwarding Data harzards even with Forwarding Stall Stalling Hardware Stalling Hardware Control Hazards Control Hazards: Original Pipeline Control Hazard on Branches Control Hazards: Early Branch Resolution Handling Data and Control Hazards Control Forwarding and Stalling Hardware Four Branch Hazard Alternatives Branch Prediction Guess whether branch will be taken Backward branches are usually taken (loops) Perhaps consider history of whether branch was previously taken to improve the guess Good prediction reduces the fraction of branches requiring a flush Pipelined Performance Example Pipelined Performance Example Pipelined Performance Pipelined Performance Example Pipelined Performance Example Review: Exceptions Example Exception Exception Registers Handle Multicycle Operations Introduced another data hazard in Decode stage Forwarding logic: ForwardAD = (rsD !=0) AND (rsD == WriteRegM) AND RegWriteM ForwardBD = (rtD !=0) AND (rtD == WriteRegM) AND RegWriteM Stalling logic: branchstall = BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD) StallF = StallD = FlushE = lwstall OR branchstall Ideally CPI = 1 But need to handle stalling (caused by loads and branches) SPECINT2000 benchmark: 25% loads 10% stores 11% branches 2% j