[信息与通信]MB原理及信号分析.ppt

1 MB 原理及線路分析 Reference level Pulse width Cycle time Signal Circuit Design e. Rise time: Time between two specified voltage levels of a signal during its low-to high transition. (Usually from 10% to 90% of the voltage difference between HIGH-level and LOW-level) f. Fall time: Time between two specified voltage levels of a signal during its high-to-low transition. (Usually from 90% to 10% of the voltage difference between HIGH-level and LOW-level) g. Setup time: Time from set up of a specific signal to active edge of a strobe signal (such as control or clock signal). h. Hold time: Time from active edge of a strobe signal (such as control or clock signal) to end of a specific signal. Signal Circuit Design Rise time Fall time Signal Circuit Design Strobe signal (e.g. control or clock signal) setup hold time time setup time hold time Signal Circuit Design Cycle time 1 Cycle time 2 Clock jitter = DIFF (Cycle time 1, Cycle time 2) i. Clock jitter: Period difference between two cycles of a clock signal. Signal Circuit Design Clock skew Clock signal at location 1 Clock signal at location 2 j. Clock skew: Phase difference of a clock signal at different locations. Signal Circuit Design 方框图 内部逻辑图 Signal Circuit Design IC 集成电路 II. Circuit design concept 1. IC 非門 輸出 a. TOTEM-POLE: Logic state is determined by the IC itself. +5V Y “1” A A Y Signal Circuit Design b. Open-collector (or Open-drain) output: . IC current is supplied through external pull-high resistor. . Open-co