i2c slave fpga实现代码.doc

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY i2c_slave IS GENERIC ( WR_OP_MODE: STD_LOGIC :=1 ); PORT ( ----------I2C Bus-------- scl : IN STD_LOGIC ;----I2C bus clk sda : INOUT STD_LOGIC ; ---------sys clk----add sys_clk : IN std_logic; reset : IN STD_LOGIC ; ---------Logic Out------- i2c_addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); i2c_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); wrd : OUT STD_LOGIC ; ---0 write 1 read wrd_en : OUT STD_LOGIC ;---1 active i2c_scl_out : OUT STD_LOGIC ;----falling edge ---------Logic In------- i2c_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --------dv_id in-------- dv_id_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); END i2c_slave; ARCHITECTURE beh OF i2c_slave IS CONSTANT RESET_ACTIVE : STD_LOGIC := 0; CONSTANT IDLE : STD_LOGIC_VECTOR :=0001; ----Grad code CONSTANT HEADER : STD_LOGIC_VECTOR :=0011; CONSTANT ACK_HEADER : STD_LOGIC_VECTOR :=0010; CONSTANT RCV_REG_ADDR : STD_LOGIC_VECTOR :=0110; CONSTANT ACK_REG_ADDR : STD_LOGIC_VECTOR :=0111; CONSTANT RCV_DATA : STD_LOGIC_VECTOR :=0101; CONSTANT ACK_DATA : STD_LOGIC_VECTOR :=0100; CONSTANT XMIT_DATA : STD_LOGIC_VECTOR :=1010; CONSTANT WAIT_ACK : STD_LOGIC_VECTOR :=1011; ----bit counter constant CONSTANT CNT_DONE : STD_LOGIC_VECTOR :=0111; ---i2c signal SIGNAL sda_in : STD_LOGIC ; SIGNAL detect_start,detect_stop : STD_LOGIC; sIGNAL state : STD_LOGIC_VECTOR(3 DOWNTO 0); ----bit counter 0 to 7 SIGNAL bit_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL bit_cnt_ld,bit_cnt_en : STD_LOGIC ; SIGNAL addr_match : STD_LOGIC ; ---header data SIGNAL i2c_header : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL i2c_header_en : STD_LOGIC; ---shift data SIGNAL i2c_shift_data : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL i2c_shift_en : STD_LOGIC ; ---addr SIGNAL addr_flag : STD_LOGIC ; SIGNAL addr_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL get_data_flag : STD_LOGIC ; ----slave_sda SIGNAL slave_sda : STD_LOGIC ; SIGNAL sda_