4_Mask工艺.ppt

GLASS GATE Via Hole Layer Process 目的:去除Via Hole Pattern上的PR (4)Wet PR Strip ITO Layer Process GLASS GATE 目的: 为形成Pixel电极,通过Sputter进行ITO沉积 ITO是一层透明金属，是铟和锡氧化物的合金。ITO沉积400?。 (1)ITO Deposition ITO Layer Process GLASS GATE ITO MASK (EXPOSURE) GLASS GATE 目的:为形成Pixel电极,通过Photo Lithography process形成PR pattern (2)ITO Mask ITO Layer Process GLASS GATE 通过 PR形成的Pattern去除Glass上形成的ITO层以外的部分，即没有被PR覆盖者的那部分ITO (3)ITO Etch ITO Layer Process GLASS GATE 目的:通过去除PR,形成ITO pattern (4)Wet PR Strip 4 Mask Process 后的基板 GLASS GATE AlNd (3000?) MO (400?) G-SiNx:H (3500?) G-SiNx:L (500?) a-Si:L (500?) a-Si:H (1300?) n+a-Si (500?) MO (2200?) B-PVX (2200?) T-PVX (300?) Array工艺完成后的基板 GATE S/D VIA HOLE ITO ITO (400?) Layer Name Thickness CVD Dep.用Gas Description Gate Alnd\Mo 3400±10% ? Ar 信号传导线 Gate Insulator G-SiNx:H 3500±10% ? SiH4+NH3+N2 对Gate信号线进行保护和绝缘的作用 G-SiNx:L 500±10% ? Active a-Si:L 500±20% ? SiH4+H2 在TFT器件中起到开关作用 a-Si:H 1300±15% ? n+ a-Si 500±20% ? SiH4+PH3+H2 减小a-Si层与S/D信号线的电阻 MO Mo 2200±10% ? Ar S/D信号线 Passivation (PVX, Via Hole) p-SiNx 2500±350 ? SiH4+NH3+N2 对S/D信号线进行保护 ITO 铟锡氧化物合金 400±100 ? Ar+O2 信号线 4 Mask工艺的Parameter 4 Mask工艺 Array?工艺 Array 工艺是通过4Mask工艺在玻璃上形成薄膜晶体管（TFT） 和像素电极（ITO）的过程。 Deposition Cleaning Coater Exposure Light Development Etch Inspection Strip 4 Mask工艺 – Process Flow 各层 Layer Gate Active S/D Via ITO 清洗 Cleaning Initial Clean Pre Dep. Clean 2 Pre Dep. Clean 3 Pre Dep. Clean 5 薄膜沉积 Deposition Gate Dep. Multiple Dep. S/D Dep. Via Dep. ITO Dep. 光罩 Mask Gate Mask Active Mask S/D Mask Via Mask ITO Mask 刻蚀 Etch Gate Etch Active Etch S/D Etch Via Etch ITO Etch N+ Etch 剥离光刻胶 Strip Gate Strip Active Strip S/D Strip Via Strip ITO Strip 各层 Layer Gate SDT Via ITO 清洗 Cleaning Initial Cleaning Pre Dep. Clean 2 Pre Dep. Clean 5 薄膜沉积 Deposition Gate Dep. Multiple Dep. Via Dep. ITO Dep. Pre Dep. Clean 2-1 - S/D Dep. 光罩 Mask Gate Mask SDT Mask Via Mask ITO Mask 刻蚀 Etch Gate Etch S/D Wet Etch Via Etch ITO Etch Active - Ashing - Mo - N+ (Dry) 剥离光刻胶 Strip Ga