第2章Chapter 2 Organization of Computers.ppt

课件教案共享专家 /wear1981 大学英语 Computer English Chapter 2 Organization of Computers 课件教案共享专家 /wear1981 2.4 I/O Subsystem Organization and Interfacing The design of the interface circuitry for an output device, such as a computer monitor, is somewhat different than that for the input device. As shown in Figure 2-8, the tri-state buffers are replaced by a register. The tri-state buffers are used in input device interfaces to make sure that no more than one device writes data to the bus at any time. Since the output devices read data from the bus, rather that write data to it, they dont need the buffers. The data can be made available to all output devices; only the device with the correct address will read it in. 输出设备（如显示器）接口电路的设计与输入设备的设计有所不同。如图2-8所示，寄存器代替了三态缓冲器。输入设备中使用三态缓冲器是为了确保在任何时刻都只有一个设备向总线写数据，而输出设备是从总线读取数据，不是写数据，因此不需要缓冲器。数据对于所有的输出设备都可获得，但只有具有正确地址的设备才会读取它。 课件教案共享专家 /wear1981 2.4 I/O Subsystem Organization and Interfacing The load logic plays the role of the enable logic in the input device interface. When this logic receives the correct address and control signals, it asserts the LD signal of the register, causing it to read data from the systems data bus. The output device can then read the data from the register at its leisure while the CPU performs other tasks. 装载逻辑发挥着输入设备接口中使能逻辑的作用。当此逻辑获得正确的地址信号和控制信号后，它发出寄存器的LD信号，促使它从系统数据总线上读取数据。然后输出设备可以在其空闲的时候从寄存器中读取该数据，同时CPU可以执行其他的任务。 课件教案共享专家 /wear1981 2.4 I/O Subsystem Organization and Interfacing A variant of this design replaces the register with tri-state buffers. The same logic used to load the register is used to enable the tri-state buffers instead. Although this can work for some designs, the output device must read in data while the buffers are enabled. Once they are disabled, the outputs of the buffers are tri-stated and the data is no longer available to the output device. 该设计也可以用三态缓冲器代替寄存器。装载寄存器的逻辑同样用于使能三态缓冲器。虽然对于某些设计这是可行的，但是输出设备必须在缓冲器有效时读入数据。一旦缓冲器被禁止，其输出就是三态，该数据也就不再能够供输出设备使用。 课件教案共享专家 /wear1981 2.4 I/O Sub