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基于FPEG的SOC设计-mips指令系统-(verilog代码)
//-------------------------------------------------------
//基于FPEG的SOC设计
// mips.v
// Model of subset of MIPS processor described in Ch 1
//-------------------------------------------------------
// top level design for testing
module top #(parameter WIDTH = 8, REGBITS = 3)();
reg clk;
reg reset;
wire memread, memwrite;
wire [WIDTH-1:0] adr, writedata;
wire [WIDTH-1:0] memdata;
// instantiate devices to be tested
mips #(WIDTH,REGBITS) dut(clk, reset, memdata, memread, memwrite, adr, writedata);
// external memory for code and data
exmemory #(WIDTH) exmem(clk, memwrite, adr, writedata, memdata);
// initialize test
initial
begin
reset = 1; # 22; reset = 0;
end
// generate clock to sequence tests
always
begin
clk = 1; # 5; clk = 0; # 5;
end
always@(negedge clk)
begin
if(memwrite)
if(adr == 5 writedata == 7)
$display(Simulation completely successful);
else $display(Simulation failed);
end
endmodule
// external memory accessed by MIPS
module exmemory #(parameter WIDTH = 8)
(clk, memwrite, adr, writedata, memdata);
input clk;
input memwrite;
input [WIDTH-1:0] adr, writedata;
output reg [WIDTH-1:0] memdata;
reg [31:0] RAM [(1WIDTH-2)-1:0];
wire [31:0] word;
initial
begin
$readmemh(memfile.dat,RAM);
end
// read and write bytes from 32-bit word
always @(posedge clk)
if(memwrite)
case (adr[1:0])
2b00: RAM[adr2][7:0] = writedata;
2b01: RAM[adr2][15:8] = writedata;
2b10: RAM[adr2][23:16] = writedata;
2b11: RAM[adr2][31:24] = writedata;
endcase
assign word = RAM[adr2];
always @(*)
case (adr[1:0])
2b00: memdata = word[31:24];
2b01: memdata = word[23:16];
2b10: memdata = wo
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