180纳米逻辑芯片制造流程.pptVIP

018LG Process Introduction (1P6M) * Logic Circuit: 能够 展现 精确的模拟特性， SOC与IC组成的系统相比，由于SOC能够综合并全盘考虑整个系统的各种情况，可以在同样的工艺技术条件下实现更高性能的系统指标 若采用IS方法和0.35?m工艺设计系统芯片，在相同的系统复杂度和处理速率下，能够相当于采用0.25 ~ 0.18?m工艺制作的IC所实现的同样系统的性能 与采用常规IC方法设计的芯片相比，采用SOC完成同样功能所需要的晶体管数目可以有数量级的降低 ASIC: 为了满足消费者特定需求而专门设计的半导体电路 VDD IN OUT CMOS反相器 VDD Y A1 A2 与非门：Y=A1A2 基本电路结构：MOS器件结构 基本电路结构：CMOS 18LG adopt 27 Photo mask , if include ESD layer AA/Poly/CT/ M1~M5/ V1~V5 use DUV scanner (13 layer) “ DARC” Cap on Critical layer and Top M6 Poly M1~M5 adopt OPC (optical proximity correction) for line-end shorting island missing Composite Spacer (ONO) PSM method apply on CT layer Cobalt salicide process Low K IMD layer (FSG) 0.18um Process Features Outline 1. STI/Trench Isolation 2. Well Definition/Vt Adjust 3. Gate Formation 4. N/PMOS Formation 5. Salicide Formation 6. ILD Layer / Contact CT (FEOL: device) 7. Metal / VIA 8. Top Meta l Via 9. Passivation (BEOL: interconnect) WAFER START RS CHECK P type 8 ~ 12 ohm-cm, non-EPI wafer Start OX 100A dry 1. PR isolation 2. Prevent the laser mark Si recast 3. Surface cleanness 4. Backside oxidation trap the metal ion ZERO Photo For ASML stepper system global Wafer alignment ZERO Fully dry etch (OX 100A + SI 1200+-200 A) ZERO Strip 1625? Nitride 110? PAD Oxide Wafer Mark (For Wafer alignment) Scrubber Clean (TJBB) Start oxide RM NLH320A (50:1 HF 350 sec) Meas: Ox RM THK (25~35A) AA OX Pre-cln NCR1DH75ARCAM Pad oxide 110+-7A/ 920oC dry O2 As buffer layer to release stress, due to SIN and Si different lattice constant Nitride DEP (w/I scrubber ) 1625+- 100A / 760oC Wafer Start STOP LAYER of STI CMP SiON DEP(CVD) FE DARC320 (w/I scrubber ) AA Photo (120 layer) AA Etch (5800A) SiN/Ox+Si etch ( 80 +-2degree) AA Asher