集成电路课程设计实习内容幻灯片.pptVIP

集成电路课程设计 7月15~25日：集成电路课程设计 7月26~28日：撰写课程设计报告 集成电路课程设计题目 1. DESIGN FLIP-FLOP 2. DESIGN A CMOS 8-BIT ALU 3. DESIGN A CMOS 8-BIT ACCUMULATOR 4. DESIGN A CMOS 8-BIT MULTIPLIER 5. DESIGN A 8-BIT BIDIRECTIONAL SHIFT REGISTER 6. DESIGN A SYNCHRONOUS 8-BIT UP AND DOWN COUNTER 1必做（已做），2~6选作1个或自拟题目 集成电路课程设计 A Pseudo-Random Code Generator 8-bit binary divider CRC (cyclic redundancy checker ) . 7x4 Signed Parallel Division Circuit Automobile Locking Control System Programmable counter 参考电路 DFF ALU FULL ADDER N- BIT ADDER MULTIPLIER DFF DFF DFF C2MOS DFF TSPC Register ALU 4 4 4 4 4 AU LU MUX A B F 0 1 S C-1 C3 S0 S1 S2 Full Adder FULL ADDER SCHEMATIC Complimentary Static CMOS Full Adder FULL ADDER SCHEMATIC The Mirror Adder CMOS TG Full Adder Circuit Sum Cout A B Cin np-CMOS Adder Circuit B0 C0 C0 C0 !C1 !Sum0 B0 A0 A0 B0 B0 A0 A0 CLK CLK !CLK !CLK C2 Sum1 !A1 !A1 !B1 !B1 !A1 !A1 !B1 !B1 !C1 !C1 !CLK !CLK CLK CLK 1 ? x 0 ? x 0 ? x 1 ? x 0 ? x 0 ? x 1 ? x 1 ? x N- bit Adder The Ripple-Carry Adder N- bit Adder 超前进位加法器（进位逻辑） N- bit Adder Ripple-Carry Adder LookAhead Carry-Bypass Adder Carry-Select Adder MULTIPLIER The Array Multiplier MULTIPLIER Carry-Save Multiplier How to Get Started Find relevant reading materials. Develop a set of specifications that meet the requirements of the chosen application Make a high level rough sketch Divide and conquer Make a schedule and stick to it 课程设计报告要求 摘要 选题意义、背景，基本理论，方案选择 设计详细内容 ASIC设计流程 代码描述及仿真向量 仿真验证（Verilog XL 或 NC-lanch） 逻辑综合 布局布线 版图生成 DRC，EXTRACT，LVS 定制设计流程 电路原理及电路设计 电路仿真验证（Verilog XL 或 NC-lanch） 版图设计 DRC，EXTRACT，LVS 最高工作频率分析 结论（功能、面积、功耗、延时） Some Final Tips Start early; don’t leave anything until last minute. Periodically save backups. Keep track of what needs to be turned in as you go along. Some Design Tips Make everything modular, and test often at every step. Try to keep everything a standard rectangular shape, including final design. Using Euler paths to create efficient layouts for complex gates is better than