计算机组织与结构课件全分单元Ch04章节幻灯片.ppt

* * * * * * * * * * * * * * * 5.Line Size Line size=block size Simple, a large block size(same as line size) may rise the hit in ratio But heavy traffic to bus 行的大小 Page119 尺寸大的行，可以增加命中率，但是传输过程中对总线的压力增大。 6.Number of Caches Multilevel Caches —on chip cache(片内Cache),or board cache(板上Cache) —CPU,L1 Cache,L2 Cache,Memory ——1:1——10:2 — 100:50（速度） Unified versus Split Caches —on-chip cache holds data instructions —Unified cache , dynamic adjust the size of data or instruction by Hit On Radio —Split cache:data writes back memory, but instructions does not …… Cache数目 Page119 多级Cache 统一和分立Cache Unified Cache §4.4 Pentium 4 Cache and Power PC Cache 80386 – no on chip cache 80486 – a single on-cache of 8KBytes using 16 byte lines and four way set associative organization Pentium (all versions) – two on chip L1 caches Data instructions Pentium 4 – L1 caches(Data Cache Instruction Cache) 8k bytes(Data Cache) 64 byte lines four way set associative L2 cache Feeding both L1 caches 256k 128 byte lines 8 way set associative Page121 Pentium 4 Diagram (Simplified) L1指令Cache L1数据Cache L2 Cache Page122 Power PC Cache Organization 601 – single 32kb 8 way set associative 603 – 16kb (2 x 8kb) two way set associative 604 – 32kb 620 – 64kb G3 G4 64kb L1 cache(Data Cache Instruction Cache) 8 way set associative(比pentium4(32k)容量大) 256k, 512k or 1M L2 cache two way set associative(组数不大) Page123 PowerPC G4 Page124 L1指令Cache L1数据Cache L2 Cache ※Exercise — Set Associative Mapping A four-way set associative cache has 64k words,main memory has 256M words and divided 32M blocks(12 points) 1.Show the mapping format. 2.Where in the cache is the data from memory location FDB9753H?(when read from memory). 3.Where in the memory is the data from cache set number 09DH and tag value 1357H?(when write to memory). Analyze A four-way set associative cache has 64k words,main memory has 256M words and divided 32M blocks four-way: 4 lines/set Cache size= 64k words Memory size= 256M words ==RA