计算机组织与结构课件全分单元Ch072章节幻灯片.pptVIP

* * * * * Stack 堆栈 —Special area in main memory 存储器中的一个特点区域 —“Last-In-First-Out” “后进先出 ” Stack Pointer (SP) 堆栈指针 — be the register of CPU —Save the address of stack’s top 始终指向栈顶 Program Sate Word(PSW) 程序状态字 —In the PSW register of CPU —Save the state of result in arithmetic logical operation Program Counter (PC) 程序计数器 —Save the address of next instruction to be executed 补充知识： PC PC SP SP (4) (5) (8) 中断服务例程 General PSW PSW (0) (6) (7) (9) Y(?) (1)- (2)-(3) register register General (10)- Page211 Design Issues 设计问题 How do you identify the module issuing the interrupt? How do you deal with multiple interrupts? Page212 Identifying Interrupting Module (1) Different line for each module 多条中断线 PC Limits number of devices Software poll 软件轮询 CPU asks each module in turn Slow Identifying Interrupting Module (2) Daisy Chain or Hardware poll 菊花链(硬件轮询, 向量) Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine Bus Master 总线主控(向量) Module must claim the bus before it can raise interrupt Multiple Interrupts Each interrupt line has a priority Higher priority lines can interrupt lower priority lines Page213 Example - PC Bus 80x86 has one interrupt line 8086 based systems use one 8259A interrupt controller 8259A has 8 interrupt lines Page213 Sequence of Events 8259A accepts interrupts 8259A determines priority 8259A signals 8086 (raises INTR line) CPU Acknowledges 8259A puts correct vector on data bus CPU processes interrupt ※§7.5 Direct Memory Access(DMA) Interrupt driven and programmed I/O require active CPU intervention(干涉) Transfer rate is limited CPU is tied up(占用) DMA is the answer Page216 直接存储器存取 DMA Function Additional Module (hardware) on bus DMA controller takes over from CPU for I/O Page217 Issue read block command to I/O module Read status Of DMA module Do something else Interrupt CPU—DMA DM