计算机组织与结构课件全分单元Ch121章节幻灯片.ppt

24 27 28 30 31 33 35 William Stallings Computer Organization and Architecture6th Edition Chapter 12 CPU Structure CPU结构和功能 and Function §12.1 CPU Organization CPU must do: Fetch instructions Interpret instructions(Decode) Fetch data Process data Write(Store) data Page 412 CPU With Systems Bus Page 413 CPU CPU Internal Structure Page 414 状态标志 移位器 求补器 算术布尔逻辑 §12.2 Registers Organization CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs Top level of memory hierarchy(Chapter4) —Registers in the top —Faster access time —greater cost per bit —smaller capacity Page 414 Page100 Chapter10 Registers in CPU perform two roles User Visible Registers Control Status Registers Page 414 1.User Visible Registers General Purpose —Mean that they can contain operand or address Data —e.g.Accumulator Address —e.g.Segment Condition Codes(in PSW) —Can not (usually) be set by programs Page 415 Several design issues (1) Whether to use completely GP registers or to specialize their use Make them general purpose Increase flexibility and programmer options Increase instruction size complexity Make them specialized Smaller (faster) instructions Less flexibility Page 415 (2)How Many GP Registers? Between 8 - 32 Fewer = more memory references See also RISC (3)How length? Large enough to hold full address Large enough to hold full word 32bits 2. Control Status Registers Most of these are not visible , not operational to the user Four registers are essential to instruction execution： —Program Counter(PC) —Instruction Register(IR) —Memory Address Register(MAR) —Memory Buffer Register(MBR) Revision: what do these all do? ( See page 416 ) Page 416 Program Status Word(PSW) A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor(管理 ):Indicates whether CPU is executing in s