8.21_自动售货机控制系统设计介绍.ppt

8.21 自动售货机控制系统设计;设计要求;系统组成;系统组成方框图 ;;自动售货机VHDL程序与仿真 ;自动售货机VHDL程序;architecture behav of AUTO is type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0); signal ram :ram_type; --定义RAM signal item: std_logic_vector(1 downto 0); --商品种类 signal coin: std_logic_vector(3 downto 0); --币数计数器 signal pri,qua:std_logic_vector(3 downto 0); --商品单价、数量 signal clk1: std_logic; --控制系统的时钟信号 begin ;; elsif finish=1 then --结束交易，退币（找币） if coin“0001” then act10=‘1’;coin=coin-2; --此IF语句完成找币操作 elsif coin0000 then act5=1; coin=coin-1; else act5=0; act10=0; end if; elsif get=0 then act=0000; for i in 4 to 7 loop pri(i-4)=ram (conv_integer(item))(i); --商品单价的读取 end loop; for i in 0 to 3 loop quan(i):=ram(conv_integer(item))(i); --商品数量的读取 end loop; end if; end if; qua=quan; end process com;;m32:process(clk) --此进程完成对32Mhz的脉冲分频 variable q: std_logic_vector( 24 downto 0); begin if clkevent and clk=1 then q:=q+1; end if; if q=111111111111111111111111 then clk1=1; else clk1=0; end if; end process m32;;;code1: process (coin) --钱数的BCD到七段码的译码 Begin case coin is when 0000=y0=0000001; when 0001=y0=1001111; when 0010=y0=0010010; when 0011=y0=0000110; when 0100=y0=1001100; when 0101=y0=0100100; when 0110=y0=0100000; when 0111=y0=0001111; when 1000=y0=0000000; when 1001=y0=0000100; when others=y0=1111111; end case; end process;;code2: process (qua) --单价的BCD到七段码的译码 Begin case qua is when 0000=y1=0000001; when 0001=y1=1001111; when 0010=y1=0010010; when 0011=y1=0000