Verilog设计的层次以及风格.ppt

7.10 RAM存储器设计 生成一个新的宏模块 设置输出文件的类型、目录和名字 定制RAM模块的数据宽度和深度 指定RAM模块的初始化数据文件 【例7.46】用文本方式调用RAM存储器模块 module ram_dy(addr,clk,din,wr,qout); //端口定义 input[6:0] addr; input clk; input[7:0] din; input wr; output[7:0] qout; myram u1(address(addr),.clock(clk),.data(din),.wren(wr),.q(qout)); //元件例化 endmodule 7.11 FIFO缓存器设计 用MegaWizard Plug-in Manager工具定制FIFO模块 定制FIFO模块的端口 设定速度优先还是面积优先 FIFO模块的功能仿真波形图（Quartus Ⅱ） 定制FIFO模块的数据宽度和深度 begin // 步长大于1 k = 127 / i; m = i * k; // 最后1个样点 address = address + i; if( address = m ) // 完成1个周期 address = 0; end end 1: // 产生锯齿波 begin if( control == 0 ) address = 0; if( control == 2 ) address = 256; if( control == 3 ) address = 384; if( address 128 ) address = 128; else begin if( i == 0 || i == 1 ) begin address = address + 1; if( address == 255 ) address = 128; end else begin k = 127 / i; m = i * k; address = address + i; if( address = ( m + 128 ) ) address = 128; end end 2: // 产生方波 begin if( control == 0 ) address = 0; if( control == 1 ) address = 128; if( control == 3 ) address = 384; if( address 256 ) address = 256; else begin if( i == 0 || i == 1 ) begin address = address + 1; if( address == 383 ) address = 256; end else begin k = 127 / i; m = i * k; address = address + i; if( address = ( m + 256 ) ) address = 256; end end 3: // 产生三角波 begin if( control == 0 ) address = 0; if( control == 1 ) address = 128; if( control == 2 ) address = 256; if( address 384 ) address = 384; else begin if( i == 0 || i == 1 ) begin address = address + 1; if( address == 511 ) address = 384; end else begin k = 127 / i; m = i * k; address = address + i; if( address = ( m + 384 ) ) address = 384; end end end endcase end endmodule 7.9.2 波形数据ROM定制 1. 设计ROM初始化数据文件 mif （Memory Initialization File） hex