《高性能处理器体系结构》Data-Level Parallel Architecture数据并行体系结构(87P).ppt

* * Intel MMX: Basics Most multimedia apps work on short integers Pack data into 64-bit words Bytes 8bits Words 16 bits Double words 32 bits Operate on packed data like short vectors (SIMD) USTC CS AN Hong * * MMX Extension MMX registers: 64-bit MM0 to MM7 shared with FP registers R0, R7, has side-effect on FPU state, only use for operands Four MMX data types: 64-bit / 32-bit access mode from memory to MMX registers SIMD techniques for arithmetic/logical operations on bytes, words, doublewords from/to 64-bit registers 0 63 Packed Byte 8x8 Packed Word 16x4 Packed Doubleword 32x2 Quadword 64 MMX Register USTC CS AN Hong * * MMX Instruction Set MMX instruction set consists of 57 instructions, group into 7 categories: Arithmetic instructions Data transfer instructions Comparison instructions Conversion instructions Logical instructions Shift instructions Empty MMX state instruction (EMMS) Minimizes ISA changes Can improve performance up to 8x (in theory) benchmark perf not 8x, but very good and gives customers another reason to consider their current PC obsolete. USTC CS AN Hong * * MMX Instruction Set USTC CS AN Hong * * MMX Instruction Set - Arithmetic Overflow/underflow for Wraparound: truncated; for Saturation: set to the maximum/minimum value, useful for graphics Packed multiplication: perform four multiplications on pairs of 16-bit operands, producing 32-bit results; PMULHW / PMULLW writes high-order / low-order 16 bits of results to destinations Packed multiply add: multiply 4 16-bit pair of sources and destinations; four 32-bit results are summed in pairs Arithmetic Wraparound Signed saturation Unsign saturation Addition PADD(b,w,d) PADDS(b,w) PADDUS(b,w) Subtraction PSUB(b,w,d) PSUBS(b,w) PSUBUS(b,w) Multiplication PMUL(lw,hw) Multiply and Add PMADDWD USTC CS AN Hong * * Example:Packed Multiply Add 4 multiplications and 2 adds in one PMADDWD PMADDWD produces 2 DW (32 bits) results Useful inst. for many media and signal applicati