ADS1255IDBT特点.doc

ADS1255IDBT特点:?????海力士ADS1255IDBT -的H / L系列专为高速可达133MHz的引用，并提供全面上升，均同步操作的差分时钟输入下降沿。虽然所有的地址和控制输入上的时钟，数据，数据和写入数据频闪灯口罩的上升沿锁存输入被采样的上升沿和下降沿它。数据路径内部流水线和2位预取，以达到非常高的带宽。所有输入和输出电压值与SSTL_2兼容。高速频率，可编程的延迟和突发长度允许器件工作在各种高性能的内存系统。ADS1255IDBT(绝对)最大额定值:?????描述ADS1255IDBT是一个低电压CMOS单总线缓冲器与亚微米硅栅与双层金属布线C2MOS技术制作而成。三态控制输入G有被设置低到高阻抗放入状态输出。ADS1255IDBT引脚说明:?????当P0.0的和P0.1从标准TTL特点不同，他们是亲密的管脚不够仍然可以用作通用I / O的尼克酸（P0.2）的C语言编程电压输入。 （见注2。）光电/铂族金属（P0.1在）C输入的指定验证模式（输出使能）或程序模式。光电/铂族金属= 1输出启用（验证模式）。光电/铂族金属= 0程序模式。 ASEL（P0.0的）C输入，显示哪些EPROM的地址位被应用到端口3。 ASEL = 0低字节地址在端口3可用。 ASEL = 1高地址字节的可用端口3（仅3个最低有效位的使用）。ADS1255IDBT Features:Hynix ADS1255IDBT-H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. ADS1255IDBT(Absolute) Maximum Ratings:DESCRIPTION The ADS1255IDBT is a low voltage CMOS SINGLE BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. 3-STATE control input G has to be set LOW to place the output into the high impedance state. ADS1255IDBT Pinout:While P0.0 anbd P0.1 differ from standard TTL characteristics, they are close enough for the pins to still be used as general-purpose I/O. VPP (P0.2) C Programming voltage input. (See Note 2.) OE/PGM (P0.1) C Input which specifies verify mode (output enable) or the program mode. OE/PGM = 1 output enabled (verify mode). OE/PGM = 0 program mode. ASEL (P0.0) C Input which indicates which bits of the EPROM address are applied