FPGA_verilog入门学习.docx

标签： FPGA??verilog??自学??FPGA_verilog入门学习本人FPGA学习的第一个程序：数字电路三八译码器（具有使能端EN）。源代码：/*------------------------------------------------------------------------------------ Filename ﹕ decoder3_8.v-- Author :songjun-- Description ﹕3-8线译码器组合逻辑-- Revision History ﹕11-1-21-- Revision 1.0-------------------------------------------------------------------------------------*/module decoder3_8(out,in,en);output[7:0] out;input[2:0] in;input en;reg[7:0] out;always@(in)begin?if(en)?begin??case(in)??3d0:out=8??3d1:out=8??3d2:out=8??3d3:out=8??3d4:out=8??3d5:out=8??3d6:out=8??3d7:out=8??????? endcase?end?else out=8bzzzzzzzz;endendmodule仿真图：??? ?图1? 具有芯片延时?　　　　　　　　图2? 无芯片延时学习FPGA的第二个程序（夏闻于老师那本书真是不错让我一下子豁然开朗）带使能和复位的十进制计数器verilog源代码/*------------------------------------------------------------------------------------ Filename ﹕ conter_10.v-- Author :songjun-- Description ﹕10 disables counter-- Revision History ﹕11-1-26-- Revision 1.0-------------------------------------------------------------------------------------*/module conter_10(clk,q,en,rst);input clk,en,rst;output [3:0] q;reg [3:0] q;always@(posedge clk)begin??? if(en==1)??if(rst==1)??? //if and else must the same???q=4b0000;??else???if(q9)????q=q+1;???else????q=4b0000;?else????q=4bzzzz;endendmodule?时序仿真图