pwm寄存器.doc

PWM Enable（可能） Register (PWME) PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 0 Pulse width（脉冲宽度） channel 7 is disabled. 1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when its clock source begins its next cycle. PWM Polarity（极性） Register (PWMPOL) PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is reached. 1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is reached. PWM Clock Select（计时器选择） Register (PWMCLK) PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 Pulse Width Channel 7 Clock Select 0 Clock B is the clock source for PWM channel 7. 1 Clock SB is the clock source for PWM channel 7. PWM Prescale（预分频） Clock Select Register (PWMPRCLK) PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0 Prescaler Select for Clock B—Clock B is one of two clock sources which can be used for channels 2, 3, 6, or 7. These three bits determine the rate of clock B, as shown in Table 13-5. Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or 5. These three bits determine the rate of clock A, as shown in Table 13-6. PWM Center Align（中央排列） Enable Register (PWMCAE) CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 Center Aligned Output Modes on Channels 7–0 0 Channels 7–0 operate in left aligned output mode. 1 Channels 7–0 operate in center aligned output mode PWM Control（控制） Register (PWMCTL) CON67 CON45 CON23 CON01 PSWAI PFRZ 0 0 Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8-bit PWMs. 1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity bit d