高性能处理器体系结构推测执行值预测和指令重用技术.ppt

* * Fetch Decode Issue Execute Commit Predict Value Verify if mispredicted Predicted instruction executes normally. Dependent instruction cannot commit until predicted instruction has finished executing. Computed result compared to predicted; if ok then dependent instructions can commit. If not, dependent instructions must reissue and execute with computed value. Miss penalty = 1 cycle later than no prediction. Verifying predictions * * Instruction Reuse Obtain results of instructions from their previous executions. If previous results still valid, don’t execute the instruction again, just commit the results! Non-speculative, early verification Previous results read in parallel with fetch. Reuse test in parallel with decode. Only execute if reuse test fails. Fetch Decode Issue Execute Commit Check for previous use Verify arguments are the same if reused * * How to reuse instructions? Reuse buffer Cache indexed by instruction address (PC) Stores result of instruction along with info needed for establishing reusability: Operand register names Pointer chain of dependent instructions Assume 4K entries (each entry takes 4x as much space as VPT: compare to 16K VP) 4-way set-associative. * * Reuse Scheme Dependent chain of results (each points to previous instruction in chain) Entry is reusable if the entries on which it depends have been reused (can’t reuse out of order). Start of chain: reusable if “valid” bit set; invalidated when operand registers overwritten. Special handling of loads and stores. Instruction will not be reused if: Inputs not ready for reuse test (decode stage) Different operand registers * * “predict the results of instructions based on previously seen results” “recognize that a computation chain has been previously performed and therefore need not be performed again” Value Prediction (VP) Instruction Reuse (IR) Comparing VP and IR * * Value Prediction (VP) Instruction Reuse (IR) “predict the results of instructions based on previously seen resu