基于FPGA的秒表(源程序).docVIP

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity miaobiao is port( Clock : in std_logic; Reset : in std_logic; segment_out: out std_logic_vector(6 downto 0); sweep :out std_logic_vector( 3 downto 0)); end miaobiao; architecture Behavioral of miaobiao is signal clk_1k:std_logic; signal clk_100h:std_logic; signal cnt4:integer range 0 to 3; signal data:std_logic_vector(3 downto 0); signal dout:std_logic_vector(3 downto 0); signal div,div1:std_logic_vector(26 downto 0):=(others=0); signal led1,led2,led3,led4:std_logic_vector(3 downto 0); begin process(Clock) ---100hz分频 begin if rising_edge(Clock) then div=div+1; if div=399999 then div=(others=0); end if; if div=199999 then clk_100h=1; else clk_100h=0; end if; end if; end process; process(Clock) ---1khz分频 begin if rising_edge(Clock) then div1=div1+1; if div1=39999 then div1=(others=0); end if; if div1=19999 then clk_1k=1; else clk_1k=0; end if; end if; end process; process(clk_1k) ---数码管地址扫描 begin if clk_1kevent and clk_1k=1 then if cnt4=3 then cnt4=0; else cnt4=cnt4+1; end if; end if; end process; process(cnt4) begin case cnt4 is when 0=dout=1110; when 1=dout=1101; when 2=dout=1011; when 3=dout=0111; when others=null; end case; end process; process(dout) begin case dout is----------数码管位地址相对应的输出段码信号 when 1110=data=led1; when 1101=data=led2; when 1011=data=led3; when 0111=data=led4; when others=null; end case; end process; process(clk_100h,reset) ---段显示 begin if reset=0 then led4=0000;led3=0000;led2=0000;led1=0000; elsif clk_100hevent and clk_100h=1 then case led1 is when1001=led1=0000; case led2 is when1001=led2=0000; case led3 is when1001=led3=0000; case led4