DDR2 ip核使用界面.pdf

Application Note: Virtex-5 FPGAs R High-Performance DDR2 SDRAM Interface in Virtex-5 Devices Authors: Karthi Palanisamy and Rich Chiu XAPP858 (v2.2) September 14, 2010 Summary This application note describes a 667 Mb/s DDR2 SDRAM interface implemented in a Virtex®-5 device. A customized version of this reference design can be generated using the Xilinx® Memory Interface Generator (MIG) tool. Introduction DDR2 SDRAM uses a source synchronous interface for transmission and reception of data. On a read, the data and strobe are transmitted edge aligned by the memory. To capture this transmitted data using Virtex-5 FPGAs, either the strobe and/or data can be delayed. In this design, the read data is captured in the delayed strobe domain and recaptured in the FPGA clock domain using a combination of the Input Double Data Rate (IDDR) and Configurable Logic Block (CLB) flip-flops. DDR2 SDRAM DDR2 SDRAM devices are the next generation devices in the DDR SDRAM family. DDR2 Overview SDRAM devices use the SSTL 1.8V I/O standard. The following section explains the features available in the DDR2 SDRAM devices and the key differences between DDR SDRAM and DDR2 SDRAM devices. Table 1 provides a summary of the DDR2 reference design capabilities and features described